The present invention relates generally to a semiconductor memory device and a method for making the semiconductor memory device and, more particularly, to a high density mask-type programmable read-only memory and a self-aligned silicide process used for making the high density mask-type programmable read-only memory.
Read-only memory (ROM) devices are semiconductor integrated circuits widely used in microprocessor-based systems to permanently store information even when power is off. ROM devices are particularly well suited for applications where a large volume of devices having identical data are required or for storing data that is repeatedly used. An example of such an application is the BIOS on personal computers. ROM devices store binary signals as an array of active elements that are typically programmed as part of the fabrication process by the integrated circuit manufacturer according to a customers specifications.
Conventional mask ROM includes NOR-type and NAND-type. NOR-type ROM is formed by connecting in parallel the sources and the drains of the memory transistors. Alternatively, connecting the sources and the drains of the memory transistors in series forms a NAND-type ROM.
As shown in FIGS. 1-3 fabrication of a conventional flat-cell mask ROM begins with a semiconductor silicon substrate (10) doped with P-type impurities. Buried bit lines (11) that will constitute source/drain regions are formed by implanting N-type impurities into multiple parallel strip shaped regions of the substrate. A gate oxide layer (12), typically silicon oxide formed by thermal oxidation, is then formed over the substrate (10). Gate electrodes (13) are then formed orthogonal to the buried bit lines (11), constituting word lines for the memory array of the mask ROM device. Conventional coding procedure requires that a photoresist layer (14) be applied covering the surface of the substrate (10) while leaving the coding openings (15) exposed. Impurity ions are then implanted into the exposed channel regions of the selected memory cells.
The channel regions for the memory cell transistors lie in the region of the substrate between every two adjacent bit lines beneath the word lines. The memory cell transistors are coded as either blocking or conducting. A 1 or 0 data bit can be defined as either state. If a cell is implanted with P-type impurities, the cell is set to have a high threshold voltage effectively setting the memory cell to a permanently OFF state representing, for example, the storage of binary digit of 0. Cells without implanted impurities have a low threshold voltage setting the memory cell to an ON state when the word line voltage is high representing, for example, the storage of a binary 1.
As a result of semiconductor device manufacturers striving to improve performance and reduce cost, the size of ROM devices continues to shrink while the density of ROM devices continues to increase. Conventional ROM devices, however, suffer from higher word line and bit line resistance as line width is decreased due to device miniaturization. This adversely affects the ROM device""s operational speed.
One solution to this problem is to use thin film refractory metal silicides to reduce resistance of the word lines and bit lines. Application of suicides in a Self-ALIgned siliCIDE (SALICIDE) process allows the formation of low resistance source, gate, and drain contacts which can reduce the resistance of bit lines and word lines compared to a non-silicide structure. Salicide processes, however, require additional steps to be incorporated into the manufacturing process.
U.S. Pat. No. 5,633,187 to Hsu discloses a salicide process to fabricate ROM with reduced bit line and word line resistance. The process disclosed by Hsu, however, requires the formation of two silicide layers. Hsu discloses depositing a tungsten silicide layer over the word lines followed by depositing a titanium silicide layer over the bit lines.
U.S. Pat. No. 5,712,203 to Hsu discloses another salicide process for fabricating ROM with reduced bit line resistance. Although this process requires forming only one silicide layer, only bit line resistance is reduced.
In light of the foregoing, there is a need for a salicide process that can be easily incorporated into the manufacturing process of ROM devices to provide lower bit line and word line resistance.
Accordingly, the present invention is directed to method for manufacturing a mask programmable ROM including the steps of forming an oxide layer with a thickness greater than about 1000 xc3x85 on a semiconductor substrate, forming a first mask layer over the oxide layer and patterning the first mask layer to form bit lines, removing regions of the oxide layer within the bit lines to expose the semiconductor substrate, ion implanting conductivity imparting dopants into the exposed substrate to form buried bit line regions, removing the first mask layer and forming a second mask layer, printing a code pattern and forming coding openings that expose portions of the substrate between the bit lines, removing the second mask layer, growing a gate oxide within the coding openings, depositing a conducting layer on remaining regions of the oxide layer, the buried bit line regions, and the gate oxide, forming a plurality of conducting gate structures constituting word lines for the mask ROM, and forming a salicide layer on the buried bit lines and the word lines by depositing single layer of refractory metal.
In another embodiment, the present invention is directed to a read-only memory device including a plurality of parallel bit lines formed in a substrate, a plurality of word lines perpendicular to and above the bit lines, and a plurality of memory cells formed at a junction of two adjacent bit lines and a portion of one word line. A silicide layer covers portions of the bit lines between two adjacent word lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description serve to explain the principles of the invention.